Prepare for chip design interviews, one flow step at a time.

Questions for Physical Design, RTL and Verification, placed where interviewers stop you. Every answer cites a source.
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A short puzzle from physical design, RTL or verification. Pick an answer to see why. Nothing is scored or saved.
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    Physical Design, RTL or Verification.

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    Questions sit where the interviewer cuts in.

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    Check the source, mark what you were asked, fix what’s wrong.

Short answers you can check

The direct answer first, then the common slip and the source.
Physical Design
S04 Placement

How does a timing-driven placer make critical paths shorter, and what does it cost?

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Mark what you were asked, fix what’s wrong, and talk it through in threads. Contributing is free for everyone.
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